Exemplary embodiments of the present invention relate to a technology for fabricating a semiconductor device, and more particularly, to a method for fabricating a storage node (SN) of a semiconductor device.
As the integration degree of semiconductor devices has increased, much research has been conducted to secure sufficient capacitance within a limited area. Accordingly, an SN is formed in a three-dimensional structure, for example, a cylindrical structure.
FIGS. 1A and 1B are cross-sectional views illustrating a conventional method for fabricating a semiconductor device.
Referring to FIG. 1A, an interlayer dielectric layer 12 is formed on a substrate 11 having a certain structure formed therein, and an SN contact plug 13 is formed through the interlayer dielectric layer 12. An etching stop layer 14 and an isolation layer 15 are formed on the interlayer dielectric layer 12. The isolation layer 15 and the etching stop layer 14 are selectively etched to form an open region 16 exposing the SN contact plug 13. The interlayer dielectric layer 12 and the isolation layer 15 may include an oxide layer, and the etching stop layer 14 may include a nitride layer.
Referring to FIG. 1B, an SN 17 is formed in the open region 16, and a wet dip-out process is performed to remove the isolation layer 15. Although not illustrated in FIG. 113, a dielectric layer and a plate electrode may be sequentially formed to complete a capacitor.
As the integration degree of the semiconductor devices increases, the critical dimension (CD) of the open region 16 in which the SN 17 is to be formed is continuously reduced. Accordingly, in the conventional method, it is difficult to secure a sufficient area in which the SN 17 is to be formed. As a result, the SN 17 may be formed abnormally.
To address such a concern, the isolation layer 15 at the side of the open region 16 may be additionally etched to expand the CD of the open region 16, after the open region 16 is formed. However, etching the isolation layer 15 at the side of the open region 16 by a predetermined thickness through a general etching process (dry etching or wet etching) is a very difficult process. Therefore, it is not easy to realize the etching. Furthermore, when the isolation layer 15 at the side of the open region 16 is etched, a bridge may easily occur between the adjacent open regions 16. Accordingly, the adjacent SNs 17 may be short-circuited.